A typical pipelined analog-to-digital converter (ADC) includes a plurality of cascaded sub-circuit stages each of which converts a portion of an analog input signal into one or more digital bits. In a pipelined ADC constructed based on 1.5-bit multiplying analog-to-digital converters (MADCs), except for the sub-circuit of a last stage which includes a 2-bit parallel ADC without a redundancy bit, each of the rest sub-circuit stages includes a 1.5-bit MADC which outputs a 2-bit code that may be a significant code “00”, “01” or “10”, or a redundancy code “11”. For this reason, conventional technologies generally further employ a correction circuit for eliminating outputs of redundancy code(s) and thus correcting outputs of the 1.5-bit MADCs.
FIG. 1 shows a redundancy elimination algorithm for correcting outputs of pipelined 1.5-bit MADCs. As illustrated, a totaling of 9 stages of codes are output from the sub-circuits of the pipelined ADC, including a code consisting of bits D18 and D17 of an upmost stage labeled “stage 9”, a code consisting of bits D16 and D15 of a next stage labeled “stage 8”, . . . , and a code consisting of bits D2 and D1 of a bottom stage labeled “stage 1”. After performing shift-and-add operations to these codes, 10 quantized bits Q1, Q2, . . . , and Q10 can be obtained, wherein C1, C2, . . . , and C7 are carry bits of the shift-and-add operations.
FIG. 2 is a schematic illustration of a conventional digital correction circuit for eliminating redundancy bits. As illustrated, this digital correction circuit includes a data alignment circuit formed by interconnecting a number of D-type flip-flops and a shift-and-add circuit consisting of adders. The data alignment circuit can perform different delays to the codes from different stages so as to synchronize them upon their arrival at the shift-and-add circuit. In addition, the adders can perform shift-and-add operations to the codes from different stages and thereby output quantized bits.
In the conventional digital correction circuit for eliminating redundancy bits, as the adders generally require the involvement of a rather great number of gate stages, the operations always require a long operation time.